Huawei’s New AI Chip Revolution: How SMIC’s Ascend 910B Differs from TSMC’s Version!

Recent die shots of Huawei’s HiSilicon Ascend 910 and its variant, the Ascend 910B—purportedly made by SMIC—show noticeable variations between the two, despite their similarities. Notably, the 910B incorporates fewer cores. These images were shared by Kurnalsalts, revealing details of Huawei’s HiSilicon Ascend 910, Ascend 910B, and the yet-to-be-identified Ascend 610, all designed for AI tasks.

The imagery shows the compute chiplets within the Ascend 910 and 910B, which are built using a multi-chiplet layout. Specifically, the HiSilicon Ascend 910 includes a Virtuvian AI processor, a Nimbus V3 I/O die, four stacks of HBM2E memory, and two dummy dies to ensure evenness.

The principal Virtuvian compute chiplet in the Ascend 910 contains 32 DaVinci Max AI cores (compatible with INT8 and FP16 formats) grouped into four clusters. These are linked by a 1024-bit mesh network-on-chip, operating at 2 GHz and capable of up to 128 GB/s bandwidth per core.

This chiplet also includes four 1024-bit HBM2 interfaces and five die-to-die interfaces for connections to Nimbus and PCIe I/O. The original Virtuvian chiplet was manufactured using TSMC’s N7+ fabrication process, which incorporates several EUV layers, and measures 14.6 mm × 31.25 mm, resulting in a die area of 456.25 mm^2.

In contrast, the compute chiplet of the HiSilicon Ascend 910B has dimensions of 21.32 mm × 31.22 mm and a significantly larger die area of 665.61 mm^2. The 910B reportedly includes 25 DaVinci AI cores, which @Kurnalsalts suggests might be a new iteration of the DaVinci cores, rather than the DaVinci Max cores found in the original.

Details about the enhancements in these “New DaVinci” cores are not clear, though it is assumed they are compatible with software written for the original cores.

It’s speculated that the Ascend 910B’s compute chiplet, referred to as Virtuvian B, is produced using SMIC’s N+1 technology, a suspected 7nm-class fabrication process. The considerable increase in the die size of Virtuvian B compared to the original could suggest a lower transistor density in SMIC’s N+1 process relative to TSMC’s N7+, or potentially a significant redesign of the DaVinci cores that required more space, though this latter scenario seems less likely.

Kurnalsalts also unveiled a die shot of the Ascend 610, an AI chip that combines 16 general-purpose CPU cores, eight DaVinci Max cores, “DaVinci mini” cores, and a 192-bit LPDDR5 memory interface. The specific use-case for this chip is not yet confirmed, but it may target edge devices needing robust CPU and advanced AI functionalities. There’s speculation that SMIC might also be manufacturing this chip.